Jared Smolens : research


Research Projects and Publications

My research is focused on architecting and modeling scalable RAS (reliable, available, servicable) computer systems. I am interested in computer architecture, microarchitecture, multiprocessors, performance modeling and simulation.


TRUSS: Total Reliability Using Scalable Servers
Under the direction of Babak Falsafi, James C. Hoe and Ken Mai

Please respect the copyrights on these publications.

PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers
Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe
The 13th IEEE Pacific Rim International Symposium on Dependable Computing
(PRDC'07), December 2007 [PDF]

Detecting Emerging Wearout Faults
Jared C. Smolens, Brian T. Gold, James C. Hoe, Babak Falsafi, and Ken Mai
The Third IEEE Workshop on Silicon Errors in Logic - System Effects,
(SELSE-3) April 2007 [PDF]

Fingerprinting Across On-chip Memory Interconnects
Srinivas Chellappa, Frédéric de Mesmay, Jared C. Smolens, Babak Falsafi, James C. Hoe, and Ken Mai
The Third IEEE Workshop on Silicon Errors in Logic - System Effects,
(SELSE-3) April 2007 [Paper PDF] [Poster PDF]

Reunion: Complexity-Effective Multicore Redundancy
Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe
ACM/IEEE International Symposium on Microarchitecture,
(MICRO-39), December 2006. [PDF]

The Granularity of Soft-Error Containment in Shared-Memory Multiprocessors
Brian T. Gold, Jared C. Smolens, Babak Falsafi, and James C. Hoe
2006 Workshop on System Effects of Logic Soft Errors,
(SELSE-2) April 2006, [Paper PDF] [Poster PDF]

TRUSS: A Reliable, Scalable Server Architecture
Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric Chung, Vasileios Liaskovitis, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk
IEEE Micro: Special Issue on Reliability-Aware Microarchitectures,
November-December 2005, [PDF]

Understanding the Performance of Concurrent Error Detecting Superscalar Microarchitectures
Jared C. Smolens, Jangwoo Kim, James C. Hoe, and Babak Falsafi
IEEE International Symposium on Signal Processing and Information Technology,
(ISSPIT) Invited Paper, December 2005, [PDF]

Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk
IEEE Micro Special Issue: Top Picks From Computer Architecture Conferences,
November-December 2004, [PDF] (also see full ASPLOS-XI paper below)

Efficient Resource Sharing in Concurrent Error Detecting
Superscalar Microarchitectures

Jared C. Smolens, Jangwoo Kim, James C. Hoe, and Babak Falsafi
ACM/IEEE International Symposium on Microarchitecture,
(MICRO-37), December 2004 [PDF]

Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk
International Conference on Architectural Support for Programming Languages and Operating Systems,
(ASPLOS-XI), October 2004, [PDF]


SimFlex: Fast, Accurate & Flexible Computer Architecture Simulation
Under the direction of Anastassia Ailamaki, Babak Falsafi, James C. Hoe, and Ken Mai

I am involved with the development of Flexus. Flexus is a C++-based full-system timing-accurate simulator of uni- and multiprocessor systems. I designed and implemented the detailed shared cache CMP model and coherence protocol (based on the Piranha CMP coherence protocol) and the DSM network simulator/timing model (based on the Alpha 21364/GS1280 switch).

I also work closely with students on the ProtoFlex project. ProtoFlex is an FPGA-based hybrid full-system functional simulator/emulator for modeling large-scale multiprocessors.


OpenSPARC Development

I am responsible for the Transplant project for the Sun OpenSPARC. This project is an application of the concepts in ProtoFlex that allows complete operating systems (e.g., Solaris 10) and user programs to "transplant" over to the OpenSPARC RTL model and fall back to a full-system simulator for system-level components that aren't typically part of an RTL model (such as disks and I/O). The transplant capability allows evaluation of real workloads on the highly-detailed RTL model.

Much of my thesis work involves working with various forms of architectural and microarchitectural fingerprints on the Sun OpenSPARC T1. Many thanks to Sun Microsystems for making the RTL, architectural models, and validation suites freely available to the public.

Get the source Free! OpenSPARC


Copyright © 2013 by Jared Smolens
Last modified: Sunday, 29-Jun-2008 19:08:50 PDT